Physical Verification

GlobalFoundries Singapore PTE LTD

0.18UM 3.3V/(5V)6V MCU Technology

Topological And Reliability

Design Rules

• Design Manual
  • 1.0 Purpose
  • 2.0 Scope
  • 3.0 Layout Information
  • 4.0 Topological Level Definitions
    • 4.1 Drawn layer definition and abbreviation
    • 4.2. Generated Layer and Generation rules
    • 4.3. Mask Layer Numbering
    • 4.4. Topological Truth Table for 3.3V/(5V)6V Process
  • 5.0 DFM (Design For Manufacturability) Guidelines
    • 5.1 Guidelines for polygon shapes to be avoided
    • 5.2 Guidelines for better one layout over the other
    • 5.3 Other miscellaneous DFM guidelines covered under Design rules
    • 5.4 Essential Guidelines for Analog Design
  • 6.0 Essential Tapeout Checklist
  • 7.0 Layout Rule Description
  • 8.0 Antenna Ratio Rules
  • 9.0 Bond Pad
    • 9.1 Bond Pad Rules
    • 9.2 Bond Pad Guidelines
    • 9.3 Circuit-Under-Pad (CUP) Rules
    • 9.4 Guidelines For Solder Bumping Technology
      • 9.4.1 Bump Design guidelines
      • 9.4.2 General Information
      • 9.4.3 Solder Bump Pad design guidelines
      • 9.4.4 Alignment Mark for bumping process
      • 9.4.5 Probe pad design guidelines
  • 10.0 Analog Device Related Rules
    • 10.1 P+ Poly Resistor (PRES)
    • 10.2 N+ Poly Resistor (Low SHEET RHO)
    • 10.3 HRES Poly Resistor (PHRES) (Optional with one additional mask)
    • 10.4 MIM (Metal-insulator-Metal) Capacitor (Optional)
      • 10.4.1 MIM Option A
      • 10.4.2 MIM Option B
    • 10.5 Native Vt NMOS (Optional)
    • 10.6 Match pair layout guidelines
      • 10.6.1 Devices required to be laid out as matched pair
      • 10.6.2 Matched pair layout guidelines
      • 10.6.3 Sample layout of matched pair devices
    • 10.7 DRC_BJT Mark Layer
    • 10.8 Design Rules for Dummy Exclude layers (NDMY and PMNDMY)
    • 10.9 LVS_BJT Mark Layer
    • 10.10 OTP_MK Mark Layer
    • 10.11 0.18um MCU eFuse Design Rules
    • 10.12 High Voltage LDMOS and related rules
      • 10.12.1 10V LDNMOS rules
      • 10.12.2 10V LDPMOS rules
    • 10.13 YMTP_MK Mark Layer Rules
    • 10.14 Schottky Diode
    • 10.15 NEO_EE_MK Layer
  • 11.0 SRAM Core Cells
    • 11.1 5V SRAM
    • 11.2 3.3V SRAM
  • 12.0 Scribe Line & Guard Ring Rules And Guidelines
    • 12.1 Scribe Lines
    • 12.2 Six Metal Scribe Line Guard Ring Structure
    • 12.3 Placement and Electrical Connection of Guard Ring
      • 12.3.1 Guard ring spacing to any other circuits
      • 12.3.2 Guard ring and Vss bus
      • 12.3.3 Used with Down Bond Chip
    • 12.4 Guard Ring design rule check
  • 13.0 Dummy Fill Rules And Guidelines
    • 13.1 Design rules for Dummy COMP creation.
    • 13.2 Design rules for Dummy Poly2 addition
    • 13.3 Design rules for Dummy Metal addition
  • 14.0 Reliability Related Rules And Guidelines
    • 14.1 Chip Operating Conditions
      • 14.1.1 Temperature Limits
      • 14.1.2 Power Supply Voltage Limits
      • 14.1.3 Chip Burn-in Limits
      • 14.1.4 Device Voltage Limits
        • 14.1.4.1 Voltage Limits Due to Hot Carrier Induced FET Degradation
        • 14.1.4.2. Voltage Limits Due to Gate Oxide Breakdown
    • 14.2 Electro-migration
      • 14.2.1 Current
      • 14.2.2 Temperature
    • 14.3 Latch-up Rules and Guidelines
      • 14.3.1 Core Latch-up Rules and Guidelines
      • 14.3.2 I/O Latch-up Related Rules and Guidelines
      • 14.3.3 Special Cases in the circuit
      • 14.3.4 other better layout practices (guidelines) for latch-up prevention
    • 14.4 ESD Layout Guidelines
      • 14.4.1 Design Guidelines for 3.3V LV SAB MOSFET Device
      • 14.4.2 Design Guidelines for 3.3V LV Diode
      • 14.4.3 Design Guidelines for 5V/6V HV SAB NMOS Device
      • 14.4.4 Design Guidelines for 5V/6V HV SAB PMOS Device
      • 14.4.5 Design Guidelines for 5V/6V HV Diode
    • 14.5 ESD Characterization Data
      • 14.5.1 ESD Performance from 3.3V NMOS transistor
      • 14.5.2 ESD Performance from 3.3V LV N+/PWELL diode
      • 14.5.3 ESD Performance from 3.3V LV P+/NWELL diode
      • 14.5.4. ESD Performance from 3.3V LV NWELL/PSUB diode
      • 14.5.5 ESD Performance from 5V/6V NMOS transistor
      • 14.5.6 ESD Performance from 5V/6V PMOS transistor
      • 14.5.7 ESD Performance from 5V/6V HV N+/PWELL diode
      • 14.5.8 ESD Performance from 5V/6V HV P+/NWELL diode
    • 14.6 Stress Relief Guidelines
      • 14.6.1 Rules for Location of Metal Line to be slotted
      • 14.6.2 Die Corners Guidelines
      • 14.6.3 Metal Slotting rules
  • Appendix A: Device List for Model and LVS Deck
  • Appendix B: Rules not coded