gf180mcu_fd_ip_sram__sram512x8m8wm1

gf180mcu_fd_ip_sram__sram512x8m8wm1

180nm 5V Green synchronous single port SRAM

Memory Macro IP

Datasheet

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Features

• Uses 180nm 5V Green CMOS 13.5um2 6 transistors bitcell

• 512 words X 8 bits, mux 8 Instance

• Periphery circuitry uses 5V transistors

• Operating voltage is 1.62V to 5.50V

• Operating temperature is -40 degC to 125 degC

• Minimum 3 layers of metals required: Metal1, Metal2, Metal3

• Bit write mask

• Self timed operation to reduce power

• Separate data in and data out ports

• Macro cell name: gf180mcu_fd_ip_sram__sram512x8m8wm1

1.0 Pins Description

Signal	Direction	Description
CLK	Input	Clock for the memory. Rising edge triggers operation. All inputs are latched at rising edge of the clock signal
CEN	Input	Memory Enable, Active Low. When CEN is Low, the memory is enabled. When CEN input is High, the memory is deactivated but internal states are retained. CEN must be high before 1st running cycle.
A[6:0]	Input	Address Input. This Address input port is used to address the location to be written during the write cycle and read during the read cycle.
GWEN	Input	Write Enable Input. The RAM is in write cycle when GWEN is low. The RAM is in read cycle when GWEN is high.
WEN[7:0]	Input	Bit Write Mask, Active Low. When the memory is in the write cycle, selectively write into individual outputs are controlled by WEN[7:0]. For example, if CEN, GWEN, WEN[0] are low and WEN[7:1] are high, only D[0] will write into the addressed location and D[7:1] will be ignored during CLK low to high transition.
D[7:0]	Input	Data input bus. The data input bus is used to write data into the memory location specified by address input port during the write cycle.
Q[7:0]	output	Data output bus. It outputs the contents of the memory location addressed by the Address Input signals.
VDD	Power	Power pin.
VSS	Ground	Ground pin.

2.0 Truth Table

CLK	CEN	GWEN	WEN	A	D	Q	status
	H	X	X	X	X	Hold previous data	Standby mode
	L	H	X	A	X	Q	Read mode
	L	L	H	A	D	Hold previous data	Write mode
	L	L	L	A	D	Hold previous data	Mask mode
other	X	X	X	X	X	Hold previous data	Unchanged

Note

X: don’t care

3.0 Capacitance loading ( fF ) @ TT, 25°c

Voltage	CLK	CEN	GWEN	WEN	A	D
5.0v	297.584	18.1905	49.4974	7.84667	40.1181	16.7494
3.3v	293.159	18.27	48.0111	7.64901	40.1976	16.6433
1.8v	282.301	18.2531	44.3231	7.15847	40.1807	16.0497

4.0 Power Consumption ( uW )

Condition of AC Write power is all data input pins switch and AC Read power is all address input and data output pins switch at 1MHz

4.1 5.0V Power

Condition	DC standby	AC Write	AC Read
TT corner, 5.00v, 25°c	0.00062	1017.1	908.1
SS corner, 4.50v, -40°c	0.0005	800.37	721.237
SS corner, 4.50v, 125°c	0.00062	830.363	746.438
FF corner, 5.50v, 125°c	0.0309	1293.85	1165.42
FF corner, 5.50v, -40°c	0.00075	1231.09	1109.16

4.2 3.3V Power

Condition	DC standby	AC Write	AC Read
TT corner, 3.3v, 25°c	0.00027	408.606	369.6
SS corner, 3.0v, -40°c	0.00022	330.795	301.665
SS corner, 3.6v, 125°c	0.00028	347.865	314.25
FF corner, 3.6v, 125°c	0.01212	520.218	468.576
FF corner, 3.6v, -40°c	0.00032	487.188	437.886

4.3 1.8V Power

Condition	DC standby	AC Write	AC Read
TT corner, 1.8v, 25°c	0.00008	112.563	103.176
SS corner, 1.62v, -40°c	0.00006	91.53	84.2238
SS corner, 1.62v, 125°c	0.00009	95.2317	87.8526
FF corner, 1.98v, 125°c	0.00394	144.174	130.433
FF corner,1.98v, -40°c	0.0001	133.709	121.344

5.0 AC Characteristics

The timing and power values measured from the input slew of 20ps on clock pin, 20ps on signal and output load .01pF.

5.1 5.0V AC Characteristics

Symbol	Parameter Description	SNSP Process 4.5v, -40C	SNSP Process 4.5v, 125C	Typical Process 5.0v, 25C	FNFP Process 5.5v, 125C	FNFP Process 5.5v, -40C	unit
Tcyc	Min clock period	11.8901	6.5937	6.077	4.2421	11.8901	ns
Tckh	Min clock high time	4.3873	2.3769	2.1038	1.8983	4.3873	ns
Tckl	Min clock low time	5.7235	2.2522	1.9814	1.4532	5.7235	ns
Tcsl	CEN set up time ( CEN = L )	0.4582	0.5864	0.4059	0.3889	0.3231	ns
Tchl	CEN hold time ( CEN = L )	1.2316	1.8518	1.1086	1.0775	0.7646	ns
Tcsh	CEN set up time ( CEN = H )	0.5133	0.6606	0.4354	0.411	0.3375	ns
Tchh	CEN hold time ( CEN = H )	1.2867	1.9195	1.1381	1.0996	0.779	ns
Twsl	GWEN set up time ( GWEN = L )	0.7179	1.0125	0.6271	0.5879	0.4532	ns
Twhl	GWEN hold time ( GWEN = L )	1.0255	1.4235	0.8652	0.819	0.6148	ns
Twsh	GWEN set up time ( GWEN = H )	0.6755	0.9341	0.5901	0.5622	0.433	ns
Twhh	GWEN hold time ( GWEN = H )	0.5605	0.7418	0.4925	0.4851	0.3836	ns
Twisl	WEN set up time ( WEN = L )	0.2494	0.3009	0.2391	0.218	0.2038	ns
Twihl	WEN hold time ( WEN = L )	1.0282	1.4235	0.8652	0.819	0.6148	ns
Twish	WEN set up time ( WEN = H )	0	0	0	0	0	ns
Twihh	WEN hold time ( WEN = H )	0.5605	0.7418	0.4931	0.4851	0.3837	ns
Tasl	A set up time ( A = L )	1.1558	1.5283	0.9474	0.8643	0.679	ns
Tahl	A hold time ( A = L )	0.6375	0.8184	0.5362	0.4959	0.4032	ns
Tash	A set up time ( A = H )	0.7684	1.0405	0.6332	0.5787	0.4539	ns
Tahh	A hold time ( A = H )	0.659	0.8526	0.549	0.5055	0.4089	ns
Tdsl	D set up time ( D = L )	0.0889	0.0487	0.094	0.0803	0.1129	ns
Tdhl	D hold time ( D = L )	0.5488	0.7168	0.4841	0.4914	0.3799	ns
Tdsh	D set up time ( D = H )	0.5634	0.7242	0.4577	0.3912	0.3446	ns
Tdhh	D hold time ( D= H )	0.7802	1.0735	0.6741	0.6581	0.5006	ns
Tah	Clock high to Q high	5.953	8.7955	4.8599	4.5151	3.1066	ns
Tal	Clock high to Q low	6.1438	9.0608	5.008	4.6284	3.2005	ns

5.2 3.3V AC Characteristics

Symbol	Parameter description	SNSP Process 3.0v, -40C	SNSP Process 3.0, 125C	Typical Process 3.3v, 25C	FNFP Process 3.6v, 125C	FNFP Process 3.6v, -40C	unit
Tcyc	Min clock period	12.5529	18.2595	9.2406	7.9594	5.48	ns
Tckh	Min clock high time	4.5988	5.6648	3.5802	3.2438	2.1235	ns
Tckl	Min clock low time	5.8235	5.4055	3.3345	3.7782	2.5263	ns
Tcsl	CEN set up time ( CEN = L )	0.658	0.8516	0.5415	0.497	0.4053	ns
Tchl	CEN hold time ( CEN = L )	1.9061	2.8524	1.5935	1.4765	1.0184	ns
Tcsh	CEN set up time ( CEN = H )	0.8032	1.076	0.6128	0.5388	0.4264	ns
Tchh	CEN hold time ( CEN = H )	2.0053	2.9771	1.6396	1.5031	1.037	ns
Twsl	GWEN set up time ( GWEN = L )	1.1636	1.645	0.9175	0.8121	0.5997	ns
Twhl	GWEN hold time ( GWEN = L )	1.5057	2.1524	1.1825	1.061	0.7786	ns
Twsh	GWEN set up time ( GWEN = H )	1.0276	1.4295	0.8238	0.742	0.5564	ns
Twhh	GWEN hold time ( GWEN = H )	0.7708	1.0797	0.6333	0.5996	0.4649	ns
Twisl	WEN set up time ( WEN = L )	0.3907	0.444	0.3367	0.2966	0.2662	ns
Twihl	WEN hold time ( WEN = L )	1.5067	2.1547	1.1829	1.061	0.7786	ns
Twish	WEN set up time ( WEN = H )	0	0	0	0	0	ns
Twihh	WEN hold time ( WEN = H )	0.7718	1.0797	0.6336	0.5996	0.4649	ns
Tasl	A set up time ( A = L )	1.6927	2.2075	1.2815	1.1145	0.8544	ns
Tahl	A hold time ( A = L )	0.884	1.1506	0.6974	0.6173	0.4955	ns
Tash	A set up time ( A = H )	1.2458	1.6418	0.9275	0.7869	0.6093	ns
Tahh	A hold time ( A = H )	0.9477	1.2387	0.7323	0.6397	0.5087	ns
Tdsl	D set up time ( D = L )	0.1197	0.0318	0.1189	0.1044	0.1415	ns
Tdhl	D hold time ( D = L )	0.668	0.9388	0.5924	0.576	0.4429	ns
Tdsh	D set up time ( D = H )	0.9612	1.1874	0.6739	0.5391	0.4509	ns
Tdhh	D hold time ( D= H )	1.1461	1.6115	0.9064	0.8323	0.6202	ns
Tah	Clock high to Q high	13.464	6.9234	6.0334	4.09	13.464	ns
Tal	Clock high to Q low	13.974	7.1773	6.2146	4.2304	13.974	ns

5.3 1.8V AC Characteristics

Symbol	Parameter description	SNSP Process 1.62v, -40C	SNSP Process 1.62v, 125C	Typical Process 1.8v, 25C	FNFP Process 1.98v, 125C	FNFP Process 1.98v, -40C	unit
Tcyc	Min clock period	52.6523	56.5713	23.5606	14.9291	10.9449	ns
Tckh	Min clock high time	17.8208	13.3554	11.779	7.4108	4.2538	ns
Tckl	Min clock low time	24.5821	27.1047	10.0614	6.1401	4.34	ns
Tcsl	CEN set up time ( CEN = L )	2.3698	2.4602	1.1516	0.801	0.6549	ns
Tchl	CEN hold time ( CEN = L )	7.2664	8.1591	3.8304	2.7423	2.0008	ns
Tcsh	CEN set up time ( CEN = H )	3.5768	3.5842	1.5564	0.9737	0.7969	ns
Tchh	CEN hold time ( CEN = H )	8.1164	8.8542	4.0473	2.8046	2.056	ns
Twsl	GWEN set up time ( GWEN = L )	5.3954	5.5797	2.4116	1.5291	1.1932	ns
Twhl	GWEN hold time ( GWEN = L )	6.8571	7.3684	2.7234	1.8466	1.3762	ns
Twsh	GWEN set up time ( GWEN = H )	3.7876	4.1535	1.8907	1.2981	1.0047	ns
Twhh	GWEN hold time ( GWEN = H )	4.1373	4.3563	1.4279	0.9502	0.7447	ns
Twisl	WEN set up time ( WEN = L )	0	0	0.5579	0.4839	0.4286	ns
Twihl	WEN hold time ( WEN = L )	6.895	7.3911	2.7323	1.8466	1.3786	ns
Twish	WEN set up time ( WEN = H )	0	0	0	0	0	ns
Twihh	WEN hold time ( WEN = H )	4.1449	4.3647	1.4331	0.9502	0.7447	ns
Tasl	A set up time ( A = L )	3.7675	4.186	2.5915	1.8749	1.4826	ns
Tahl	A hold time ( A = L )	2.4888	2.7025	1.3228	0.954	0.7737	ns
Tash	A set up time ( A = H )	3.5248	3.6466	2.1665	1.4549	1.1977	ns
Tahh	A hold time ( A = H )	3.0827	3.2603	1.5182	1.0367	0.8439	ns
Tdsl	D set up time ( D = L )	0	0	0	0.0668	0.1388	ns
Tdhl	D hold time ( D = L )	3.3868	3.4901	1.0901	0.8321	0.6123	ns
Tdsh	D set up time ( D = H )	3.1979	3.0367	1.745	0.9832	0.8835	ns
Tdhh	D hold time ( D= H )	6.0875	6.3089	2.2346	1.4269	1.1036	ns
Tah	Clock high to Q high	36.7512	40.5756	17.2992	11.3022	8.3234	ns
Tal	Clock high to Q low	39.2964	42.84	18.2016	11.7799	8.7016	ns

AC Timing Waveform Chart

6.0 Physical Dimensions

Width(um)	Height(um)	Area(um^2)
431.86	484.88	209400.2768