4.1 Drawn layer definition and abbreviation

The following layers are drawn directly on the layout system.

Drawn layers

Layer Type

Layer Name

Purpose

GDS #

Data type

Drawn

COMP (1)

Diffusion for device and interconnect

22

0

Drawn

DNWELL

Deep Nwell

12

0

Drawn

Nwell

Nwell implant

21

0

Drawn

LVPWELL

Pwell implant

204

0

Drawn

Dualgate

6V Gate Oxide

55

0

Drawn

Poly2

POLY2 gate & interconnect

30

0

Drawn

Nplus

Nplus Implant

32

0

Drawn

Pplus

Pplus Implant

31

0

Drawn

SAB

Unsalicided poly & active regions

49

0

Drawn

ESD (2)

ESD Implant (Optional)

24

0

Drawn

Contact

Metal1 to Active or Poly2 contact

33

0

Drawn

Metal1

Metal1 interconnect

34

0

Drawn

Via1

Metal2 to Metal1 contact

35

0

Drawn

Metal2

Metal2 interconnect

36

0

Drawn

Via2

Metal3 to Metal2 contact

38

0

Drawn

Metal3

Metal3 interconnect

42

0

Drawn

Via3

Metal4 to Metal3 contact

40

0

Drawn

Metal4

Metal4 interconnect

46

0

Drawn

Via4

Metal5 to Metal4 contact

41

0

Drawn

Metal5

Metal5 interconnect

81

0

Drawn

Via5

Metal 6 to Metal5 contact

82

0

Drawn

MetalTop

MetalTop interconnect

53

0

Drawn

Pad (1)

Bond pad opening

37

0

Drawn

Resistor (3)

High sheet rho P-poly resistor (Optional)

62

0

Drawn

FHRES (3)

Free high sheet rho P-POLY2 resistor

227

0

Drawn

FuseTop (3)

Top plate of MIM capacitors (Optional)

75

0

Drawn

FuseWindow_D

Metal Fuse window (Optional)

96

1

Drawn

POLYFUSE

POLY FUSE window (Optional)

220

0

Drawn

MVSD

Define LDNMOS Drain

210

0

Drawn

MVPSD

Define LDPMOS Drain

11

39

Drawn

NAT

N-channel native VT mark layer

5

0

Drawn

COMP_Dummy

COMP Dummy fill

22

4

Drawn

Poly2_Dummy

Poly2 Dummy Fill

30

4

Drawn

Metal1_Dummy (4)

Metal1 Dummy Fill

34

4

Drawn

Metal2_Dummy (4)

Metal2 Dummy Fill

36

4

Drawn

Metal3_Dummy (5)

Metal3 Dummy Fill

42

4

Drawn

Metal4_Dummy (5)

Metal4 Dummy Fill

46

4

Drawn

Metal5_Dummy (5)

Metal5 Dummy Fill

81

4

Drawn

MetalTop_Dummy (5)

MetalTop Dummy Fill

53

4

Drawn

COMP_Label (6)

LABEL drawn at active layer

22

10

Drawn

Poly2_Label (6)

LABEL drawn at poly2 layer

30

10

Drawn

Metal1_Label (6)

LABEL drawn at Metal1 layer

34

10

Drawn

Metal2_Label (6)

LABEL drawn at Metal2 layer

36

10

Drawn

Metal3_Label(6)

LABEL drawn at Metal3 layer

42

10

Drawn

Metal4_Label (6)

LABEL drawn at Metal4 layer

46

10

Drawn

Metal5_Label (6)

LABEL drawn at Metal5 layer

81

10

Drawn

MetalTop_Label (6)

LABEL drawn at MetalTop layer

53

10

Drawn

Metal1_Slot

Metal1 Slot (used to create slots in metal1)

34

3

Drawn

Metal2_Slot

Metal2 Slot (used to create slots in metal2)

36

3

Drawn

Metal3_Slot

Metal3 Slot (used to create slots in metal3)

42

3

Drawn

Metal4_Slot

Metal4 Slot (used to create slots in metal4)

46

3

Drawn

Metal5_Slot

Metal5 Slot (used to create slots in metal5)

81

3

Drawn

MetalTop_Slot

MetalTop Slot (used to create slots in metal top)

53

3

Drawn

UBMPPeri

Direct Bumping option using peripheral printing

183

0

Drawn

UBMPArray

Direct Bumping option using Array printing

184

0

Drawn

UBMEPlate

Direct Bumping option using Electroplating

185

0

Drawn

Schottky_diode

Define Schottky diode area

241

0

Drawn

ZENER

ZENER diode implant

178

0

Marking

RES_MK (1)

Resistor Mark

110

5

Marking

OPC_drc

Marking layer for OPC design rule check.

124

5

Marking

NDMY (1)

Dummy Active Exclude Mark layer

111

5

Marking

PMNDMY (1)

Dummy Poly & Metal Exclude Mark

152

5

Marking

V5_XTOR (7)

Define 5V Transistor Marking Layer

112

1

Marking

CAP_MK (8)

MIM Capacitor Marking layer

117

5

Marking

MOS_CAP_MK

MOS capacitor LVS marking

166

5

Marking

IND_MK

Inductor Mark

151

5

Marking

DIODE_MK

Diode Mark

115

5

Marking

DRC_BJT (9)

BJT marking for DRC

127

5

Marking

LVS_BJT

BJT Mark

118

5

Marking

MIM_L_MK

Min length marking layer for MIM Capacitor

117

10

Marking

Latchup_MK

Marking layer for I/O latch-up rule check

137

5

Marking

GUARD_RING_MK

Marking Layer for Scribe Line Guard Ring

167

5

Marking

OTP_MK

To define OTP area with Marking layer

173

5

Marking

MTPMARK

Multi Time Program Memory cell marking

122

5

Marking

NEO_EE_MK

NeoEE OTP area with Marking layer

88

17

Marking

SramCore (10)

SRAM Mark

108

5

Marking

LVS_RF

RF LVS Mark

100

5

Marking

LVS_Drain

RF Drain LVS Mark

100

7

Marking

IND_MK1

Inductor Mark

151

5

Marking

HVPOLYRS

High Voltage Poly2 Resistor in HV area Marking layer

123

5

Marking

LVS_IO

IO LVS Mark

119

5

Marking

PROBE_MK

Marking layer for probe pad

13

17

Marking

ESD_MK

Marking layer on ESD protection device

24

5

Marking

LVS_Source

Source LVS/DRC marking Layer

100

8

Marking

WELL_DIODE_MK

Marking layer for Nwell/Psub, LVPwell/Dnwell, DNwell/Psub diode

153

51

Marking

LDMOS_XTOR

LDMOS device mark layer

226

0

Marking

PLFUSE

Marking layer for eFUSE Link

125

5

Marking

EFUSE_MK

Marking layer for whole eFUSE Element

80

5

Marking

MCELL_FEOL_MK (13)

Marking layer to define YMTP Mcell Implant region

11

17

Marking

YMTP_MK (13)

Marking layer to define YMTP Cell and exclude NLDD region

86

17

Marking

DEV_WF_MK

LVS marking layer for Fab special purposes layout

128

17

EDAMark

Metal1_BLK

Place & Route Metal1 Blockage

34

5

EDAMark

Metal2_BLK

Place & Route Metal2 Blockage

36

5

EDAMark

Metal3_BLK

Place & Route Metal3 Blockage

42

5

EDAMark

Metal4_BLK

Place & Route Metal4 Blockage

46

5

EDAMark

Metal5_BLK

Place & Route Metal5 Blockage

81

5

EDAMark

MetalT_BLK

Place & Route MetalTop Blockage

53

5

EDAMark

PR_bndry

PR Boundary for cell, block or chip

0

0

EDAMark

MDIODE

MDiode Mark

116

5

EDAMark

Metal1_Res (11)

Metal 1 Resistor

110

11

EDAMark

Metal2_Res (11)

Metal 2 Resistor

110

12

EDAMark

Metal3_Res (11)

Metal 3 Resistor

110

13

EDAMark

Metal4_Res (11)

Metal 4 Resistor

110

14

EDAMark

Metal5_Res (11)

Metal 5 Resistor

110

15

EDAMark

Metal6_Res (11)

Metal6 Resistor

110

16

DevMark

Border

Border

63

0

Note

  1. Used in the dummy COMP, dummy poly2 & dummy metal generation algorithm (refer to dummy fill rules and guideline).

  2. ESD is optional mask to provide ESD implant for 3.3V or 5V/6V devices.

  3. Refer to analog rule section for complete list of analog-specific layers and masks.

  4. Metal1_Dummy and Metal2_Dummy are dummy fills for Metal1 and Metal2. Data type is used to differentiate between circuits and dummy Metal1 and Metal2. This separation is to facilitate generation of dummy poly2. Dummy poly2 needs to be generated when prime die poly2 density falls below poly2 density requirement. Circuit and metal dummy fill will be “OR” after dummy poly2 is generated (where applicable).

  5. Metal3_Dummy, Metal4_Dummy, Metal5_Dummy and MetalTop_Dummy are metal dummy fills. These are separated from circuit metal by using different data type.

  6. These layers are only for label drawing and not supposed to be part of the active circuits. Also these layers will be used in DRC and LVS for any wrong placement of label check.

  7. V5_XTOR is used as a marking layer to define 5V devices.

  8. CAP_MK is used to define the bottom plate of the MIM Capacitor for DRC purpose. It will also be used for LVS purposes. Refer to EDA-CAD-000-GS003 (LVS Recognition and Extraction Guideline) for more information and guidelines on LVS marking layers.

  9. DRC_BJT is used to mark BJT devices. BJT should follow LV design rule, unless state in special rules.

  10. SRAM Mark layer to mark SRAM cells for SRAM rules

  11. Metal resistor should draw Metal1_Res to Metal5_Res for LVS purpose.

  12. 3.3V OTP cell must be covered by OTP_MK marking for specific rules check.

  13. MCELL_FEOL_MK and YMTP_MK are dedicated for MTP cell implant, which is drawn by IP vendor. These layers are not supported in PDK of this version update.