2.0 Scope

2.1 This document covers rules from COMP layer to Passivation layer and scribe line layout. The reliability section provides layout guidelines for electromigration (EM), process-induced-damage (PID), latchup rules, ESD protection and stress migration. Device parameters, device models and process flow are available in separate documents.

2.2 This document also provides information on drawn layer definition, generated layer rules and mask layer numbers.

2.3 The dimensions stated in this document refer to the minimum allowed geometry or the window of allowed geometry. Deviations from these rules have to be approved by GlobalFoundries.

2.4 Refer to YI-000-XX010 for the terminology used in GlobalFoundries design rule specifications.

2.5 Two terms used in this document have the following specific meaning:

• Design Rules (“Rules” or “Layout Rules”) specify layout dimensions that meet both our Process and Electrical Parameter Specifications. As such, rules are implemented in our Design Rule Checker (DRC) runsets. Prior to design data submission using GlobalFoundries Foundry Service Request Specification (CX-008) procedure, the design must pass all DRC tests. Rule violations are required to complete Design Rule Waiver Request Procedure (CX-020) before design is accepted for tapeout.

• Design Guidelines (“Guidelines” or “Layout Guidelines”) are provided on an “as is” basis, without warranty of any kind, express or implied. These guidelines are specified to assist the reader in designing circuits for improved manufacturability and reliability. GlobalFoundries recognizes and acknowledges that other design or layout techniques for improving manufacturing and reliability exist. Therefore, guidelines are not implemented in DRC runsets, nor are they reviewed in the Desig Rule Waiver Request Procedure (CX-020).

2.6 Refer to the reference documents for information on mask sizing and alignment sequence (Bias Table), Optical Proximity Correction (OPC), Proprietary SRAM cells, and dummy COMP generation.

2.7 Use the table below for Process Identification on operating voltage selection:-

Process	Operating Voltages	PID in Fab3E
0.18um 3.3V/(5V) 6V (No MIM)	LV=3.3V, HV=5V or 6V	TH18*0019A
0.18um 3.3V/(5V) 6V (with MIM)	LV=3.3V, HV=5V or 6V	TH18*0020A

Note

“*” in PID denotes any numeric number for metal layer options.

2.8 Use the table below for processing of various metal level options for GlobalFoundries INTERNAL REFERENCE ONLY (e.g. frame structure, scribeline monitoring structures, testchip layout, etc.)

Levels of Metal	BEOL metal and via to be included
6LM	Metal1, Via1, Metal2, Via2, Metal3, Via3, Metal4, Via4, Metal5, Via5, MetalTop.
5LM	Metal1, Via1, Metal2, Via2, Metal3, Via3, Metal4, Via4, MetalTop. SKIP Metal5, Via5.
4LM	Metal1, Via1, Metal2, Via2, Metal3, Via3, MetalTop. SKIP Metal5, Via5, Metal4, Via4.
3LM	Metal1, Via1, Metal2, Via2, MetalTop. SKIP Metal5, Via5, Metal4, Via4, Metal3, Via3.
2LM	Metal1, Via1, MetalTop. SKIP Metal5, Via5, Metal4, Via4, Metal3, Via3, Metal2, Via2.

Use the table below for processing of various metal level options for DESIGN ACTIVITIES (e.g. product design-in, libraries solutions, IPs solutions etc.)

Levels of Metal	BEOL metal and via to be included
6LM	Metal1, Via1, Metal2, Via2, Metal3, Via3, Metal4, Via4, Metal5, Via5, MetalTop.
5LM	Metal1, Via1, Metal2, Via2, Metal3, Via3, Metal4, Via4, Metal5. Metal 5 must comply with MetalTop rule.
4LM	Metal1, Via1, Metal2, Via2, Metal3, Via3, Metal4. Metal 4 must comply with MetalTop rule.
3LM	Metal1, Via1, Metal2, Via2, Metal3. Metal 3 must comply with MetalTop rule.
2LM	Metal1, Via1, Metal2. Metal 2 must comply with MetalTop rule.

2.9 Use the table below for Process Identification on Select Type of Guard Ring:-

Type of Guard Ring	Guard Ring selected	PID in Fab3E
CUSTOMER_INSERT_GUARD_RING	Customer to insert guard ring	TH18*00G1A
FOUNDRY_INSERT_GUARD_RING	Foundry to insert guard ring	TH18*00G1A

Note

“*” in PID denotes any numeric number for metal layer options

2.10 Current 0.18 MCU PDK support following BEOL

No	Metal stack option
1	1P2M, TM30K
2	1P3M,TM6K, MIM Option A
3	1P3M,TM9K, MIM Option A
4	1P3M,TM11K, MIM Option A
5	1P3M,TM30K, MIM Option A
6	1P4M,TM6K, MIM Option A
7	1P4M,TM9K, MIM Option A
8	1P4M,TM11K, MIM Option A
9	1P4M,TM30K, MIM Option A
10	1P4M,TM9K, MIM Option B
11	1P4M,TM11K, MIM Option B
12	1P4M,TM30K, MIM Option B
13	1P5M,TM9K, MIM Option A
14	1P5M,TM9K, MIM Option B
15	1P5M,TM11K, MIM Option B
16	1P6M,TM9K, MIM Option B

Note

MIM option A is between 3 and 2 and option B is TM/TM-1