10.0 Analog Device Related RulesΒΆ
- 10.1 P+ Poly Resistor (PRES)
- 10.2 N+ Poly Resistor (Low SHEET RHO)
- 10.3 HRES Poly Resistor (PHRES) (Optional with one additional mask)
- 10.4 MIM (Metal-insulator-Metal) Capacitor (Optional)
- 10.5 Native Vt NMOS (Optional)
- 10.6 Match pair layout guidelines
- 10.7 DRC_BJT Mark Layer
- 10.8 Design Rules for Dummy Exclude layers (NDMY and PMNDMY)
- 10.9 LVS_BJT Mark Layer
- 10.10 OTP_MK Mark Layer
- 10.11 0.18um MCU eFuse Design Rules
- 10.12 High Voltage LDMOS and related rules
- 10.13 YMTP_MK Mark Layer Rules
- 10.14 Schottky Diode
- 10.15 NEO_EE_MK Layer