gf180mcu_fd_sc_mcu9t5v0__dlyd_4

gf180mcu_fd_sc_mcu9t5v0__dlyd_4 symbol

gf180mcu_fd_sc_mcu9t5v0__dlyd_4 schematic

gf180mcu_fd_sc_mcu9t5v0__dlyd_4 layout

DLYD_X4 is a 16 buffer delay cell with 4X drive strength

Attributes

Attribute	Value
area	93.139200 µm2

OUTPUT FUNCTIONS

Output Pin	Function
Z	I

TRUTH TABLE FOR Z

I	Z
1	1
0	0

FUNCTIONAL SCHEMATIC

PIN CAPACITANCE (pf)

Pin	Type	Capacitance (pf)
I	input	0.0026

DELAY AND OUTPUT TRANSITION TIME corresponding to min slew and load

Input Pin	Output	When Condition	Tin (ns)	Out Load (pf)	Delay (ns)	Tout (ns)
I(LH)	Z(LH)	default	0.0100	0.0010	2.2826	0.0859
I(HL)	Z(HL)	default	0.0100	0.0010	2.7913	0.2053

DYNAMIC ENERGY

Input Pin	When Condition	Tin (ns)	Output	Out Load (pf)	Energy (uW/MHz)
I	default	0.0100	Z(LH)	0.0010	2.0253
I	default	0.0100	Z(HL)	0.0010	4.2800

LEAKAGE POWER

When Condition	Power (nW)
!I	0.3397
I	0.3329