gf180mcu_fd_sc_mcu9t5v0__dlyd_2

gf180mcu_fd_sc_mcu9t5v0__dlyd_2 symbol

gf180mcu_fd_sc_mcu9t5v0__dlyd_2 symbol

gf180mcu_fd_sc_mcu9t5v0__dlyd_2 schematic

gf180mcu_fd_sc_mcu9t5v0__dlyd_2 schematic

gf180mcu_fd_sc_mcu9t5v0__dlyd_2 layout

gf180mcu_fd_sc_mcu9t5v0__dlyd_2 layout
DLYD_X2 is a 16 buffer delay cell with 2X drive strength

Attributes

Attribute

Value

area

81.849600 µm2


OUTPUT FUNCTIONS

Output Pin

Function

Z

I


TRUTH TABLE FOR Z

I

Z

1

1

0

0


FUNCTIONAL SCHEMATIC
../../../../../_images/gf180mcu_fd_sc_mcu9t5v0__dlyd_2.png
PIN CAPACITANCE (pf)

Pin

Type

Capacitance (pf)

I

input

0.0026


DELAY AND OUTPUT TRANSITION TIME corresponding to min slew and load

Input Pin

Output

When Condition

Tin (ns)

Out Load (pf)

Delay (ns)

Tout (ns)

I(LH)

Z(LH)

default

0.0100

0.0010

2.0244

0.0595

I(HL)

Z(HL)

default

0.0100

0.0010

2.2381

0.1196


DYNAMIC ENERGY

Input Pin

When Condition

Tin (ns)

Output

Out Load (pf)

Energy (uW/MHz)

I

default

0.0100

Z(LH)

0.0010

0.9891

I

default

0.0100

Z(HL)

0.0010

1.5646


LEAKAGE POWER

When Condition

Power (nW)

!I

0.2860

I

0.2818