gf180mcu_fd_sc_mcu9t5v0__dffnq_4

gf180mcu_fd_sc_mcu9t5v0__dffnq_4 symbol

gf180mcu_fd_sc_mcu9t5v0__dffnq_4 schematic

gf180mcu_fd_sc_mcu9t5v0__dffnq_4 layout

DFFNQ_X4 is a negative edge triggered D-type flip flop with 4X drive strength

Attributes

Attribute	Value
area	98.784000 µm2

TRUTH TABLE

Input		Output
D	CLKN	Q
L	↓	L
H	↓	H

FUNCTIONAL SCHEMATIC

CONSTRAINTS

Constraint Pin	Related Pin	setup(ns)	hold(ns)
D(HL)	CLKN(HL)	0.2060	0.0290
D(LH)	CLKN(HL)	0.1430	0.1090

Constraint Pin	Related Pin	Minimum Pulse Width(ns)
CLKN(LHL)	CLKN(LH)	0.3150
CLKN(LHL)	CLKN(LH)	0.2900
CLKN(HLH)	CLKN(HL)	0.3980
CLKN(HLH)	CLKN(HL)	0.4370

PIN CAPACITANCE (pf)

Pin	Type	Capacitance (pf)
CLKN	input	0.0050
D	input	0.0038

DELAY AND OUTPUT TRANSITION TIME corresponding to min slew and load

Input Pin	Output	When Condition	Tin (ns)	Out Load (pf)	Delay (ns)	Tout (ns)
CLKN(HL)	Q(LH)	D	0.0100	0.0010	0.6450	0.0357
CLKN(HL)	Q(HL)	!D	0.0100	0.0010	0.5884	0.0415

DYNAMIC ENERGY

Input Pin	When Condition	Tin (ns)	Output	Out Load (pf)	Energy (uW/MHz)
CLKN	D	0.0100	Q(LH)	0.0010	1.7233
CLKN	!D	0.0100	Q(HL)	0.0010	1.7311
D(LH)	!CLKN	0.0100	n/a	n/a	0.0084
D(LH)	CLKN	0.0100	n/a	n/a	0.1962
CLKN(LH)	!D	0.0100	n/a	n/a	0.2588
CLKN(LH)	D	0.0100	n/a	n/a	0.2582
CLKN(HL)	!D	0.0100	n/a	n/a	0.4076
CLKN(HL)	D	0.0100	n/a	n/a	0.4085
D(HL)	!CLKN	0.0100	n/a	n/a	0.0835
D(HL)	CLKN	0.0100	n/a	n/a	0.2980

LEAKAGE POWER

When Condition	Power (nW)
!CLKN&!D	0.5727
CLKN&!D	0.4915
!CLKN&D	0.5965
CLKN&D	0.4850