gf180mcu_fd_sc_mcu9t5v0__dffnq_1

gf180mcu_fd_sc_mcu9t5v0__dffnq_1 symbol

gf180mcu_fd_sc_mcu9t5v0__dffnq_1 schematic

gf180mcu_fd_sc_mcu9t5v0__dffnq_1 layout

DFFNQ_X1 is a negative edge triggered D-type flip flop with 1X drive strength

Attributes

Attribute	Value
area	84.672000 µm2

TRUTH TABLE

Input		Output
D	CLKN	Q
L	↓	L
H	↓	H

FUNCTIONAL SCHEMATIC

CONSTRAINTS

Constraint Pin	Related Pin	setup(ns)	hold(ns)
D(HL)	CLKN(HL)	0.2060	0.0060
D(LH)	CLKN(HL)	0.1320	0.1030

Constraint Pin	Related Pin	Minimum Pulse Width(ns)
CLKN(LHL)	CLKN(LH)	0.3150
CLKN(LHL)	CLKN(LH)	0.2780
CLKN(HLH)	CLKN(HL)	0.3290
CLKN(HLH)	CLKN(HL)	0.3490

PIN CAPACITANCE (pf)

Pin	Type	Capacitance (pf)
CLKN	input	0.0051
D	input	0.0039

DELAY AND OUTPUT TRANSITION TIME corresponding to min slew and load

Input Pin	Output	When Condition	Tin (ns)	Out Load (pf)	Delay (ns)	Tout (ns)
CLKN(HL)	Q(LH)	D	0.0100	0.0010	0.5565	0.0378
CLKN(HL)	Q(HL)	!D	0.0100	0.0010	0.5012	0.0380

DYNAMIC ENERGY

Input Pin	When Condition	Tin (ns)	Output	Out Load (pf)	Energy (uW/MHz)
CLKN	D	0.0100	Q(LH)	0.0010	0.9838
CLKN	!D	0.0100	Q(HL)	0.0010	0.8891
D(LH)	!CLKN	0.0100	n/a	n/a	0.0086
D(LH)	CLKN	0.0100	n/a	n/a	0.1984
CLKN(LH)	!D	0.0100	n/a	n/a	0.2587
CLKN(LH)	D	0.0100	n/a	n/a	0.2583
CLKN(HL)	!D	0.0100	n/a	n/a	0.4081
CLKN(HL)	D	0.0100	n/a	n/a	0.4086
D(HL)	!CLKN	0.0100	n/a	n/a	0.0861
D(HL)	CLKN	0.0100	n/a	n/a	0.3015

LEAKAGE POWER

When Condition	Power (nW)
!CLKN&!D	0.4915
CLKN&!D	0.4103
!CLKN&D	0.5192
CLKN&D	0.4078