gf180mcu_fd_sc_mcu7t5v0__latq_1

gf180mcu_fd_sc_mcu7t5v0__latq_1 symbol

gf180mcu_fd_sc_mcu7t5v0__latq_1 schematic

gf180mcu_fd_sc_mcu7t5v0__latq_1 layout

LATQ_X1 is a positive D-latch, 1X drive strength

Attributes

Attribute	Value
area	43.904000 µm2

TRUTH TABLE

Input		Output
D	E	Q
L	H	L
H	H	H
X	L	Q

FUNCTIONAL SCHEMATIC

CONSTRAINTS

Constraint Pin	Related Pin	setup(ns)	hold(ns)
D(LH)	E(HL)	0.1660	-0.0860
D(HL)	E(HL)	0.5610	-0.3950

Constraint Pin	Related Pin	Minimum Pulse Width(ns)
E(LHL)	E(LH)	0.6120
E(LHL)	E(LH)	0.4170

PIN CAPACITANCE (pf)

Pin	Type	Capacitance (pf)
E	input	0.0037
D	input	0.0030

DELAY AND OUTPUT TRANSITION TIME corresponding to min slew and load

Input Pin	Output	When Condition	Tin (ns)	Out Load (pf)	Delay (ns)	Tout (ns)
E(LH)	Q(LH)	D	0.0100	0.0010	0.5578	0.0579
E(LH)	Q(HL)	!D	0.0100	0.0010	0.4988	0.0766
D(LH)	Q(LH)	E	0.0100	0.0010	0.3327	0.0580
D(HL)	Q(HL)	E	0.0100	0.0010	0.4429	0.0774

DYNAMIC ENERGY

Input Pin	When Condition	Tin (ns)	Output	Out Load (pf)	Energy (uW/MHz)
D	E	0.0100	Q(LH)	0.0010	0.3062
D	E	0.0100	Q(HL)	0.0010	0.4620
E	D	0.0100	Q(LH)	0.0010	0.4499
E	!D	0.0100	Q(HL)	0.0010	0.5495
E(LH)	!D	0.0100	n/a	n/a	0.1273
E(LH)	D	0.0100	n/a	n/a	0.1247
D(LH)	!E	0.0100	n/a	n/a	-0.0198
E(HL)	!D	0.0100	n/a	n/a	0.2239
E(HL)	D	0.0100	n/a	n/a	0.2283
D(HL)	!E	0.0100	n/a	n/a	0.0218

LEAKAGE POWER

When Condition	Power (nW)
!D&!E	0.3042
D&!E	0.3454
!D&E	0.2478
D&E	0.2423