gf180mcu_fd_sc_mcu7t5v0__dlyd_2

gf180mcu_fd_sc_mcu7t5v0__dlyd_2 symbol

gf180mcu_fd_sc_mcu7t5v0__dlyd_2 schematic

gf180mcu_fd_sc_mcu7t5v0__dlyd_2 layout

DLYD_X2 is a 16 buffer delay cell, 2X drive strength

Attributes

Attribute	Value
area	79.027200 µm2

OUTPUT FUNCTIONS

Output Pin	Function
Z	I

TRUTH TABLE FOR Z

I	Z
1	1
0	0

FUNCTIONAL SCHEMATIC

PIN CAPACITANCE (pf)

Pin	Type	Capacitance (pf)
I	input	0.0028

DELAY AND OUTPUT TRANSITION TIME corresponding to min slew and load

Input Pin	Output	When Condition	Tin (ns)	Out Load (pf)	Delay (ns)	Tout (ns)
I(LH)	Z(LH)	default	0.0100	0.0010	2.2425	0.0525
I(HL)	Z(HL)	default	0.0100	0.0010	2.4108	0.0959

DYNAMIC ENERGY

Input Pin	When Condition	Tin (ns)	Output	Out Load (pf)	Energy (uW/MHz)
I	default	0.0100	Z(LH)	0.0010	0.8305
I	default	0.0100	Z(HL)	0.0010	1.1565

LEAKAGE POWER

When Condition	Power (nW)
!I	0.2852
I	0.2815