gf180mcu_fd_sc_mcu7t5v0__dffq_1

gf180mcu_fd_sc_mcu7t5v0__dffq_1 symbol

gf180mcu_fd_sc_mcu7t5v0__dffq_1 symbol

gf180mcu_fd_sc_mcu7t5v0__dffq_1 schematic

gf180mcu_fd_sc_mcu7t5v0__dffq_1 schematic

gf180mcu_fd_sc_mcu7t5v0__dffq_1 layout

gf180mcu_fd_sc_mcu7t5v0__dffq_1 layout

DFFQ_X1 is a poistive edge triggered D-type flip flop, 1X drive strength


Attributes

Attribute

Value

area

63.660800 µm2


TRUTH TABLE

Input

Output

D

CLK

Q

L

L

H

H


FUNCTIONAL SCHEMATIC
../../../../../_images/gf180mcu_fd_sc_mcu7t5v0__dffq_1.png
CONSTRAINTS

Constraint Pin

Related Pin

setup(ns)

hold(ns)

D(LH)

CLK(LH)

0.2180

0.0400

D(HL)

CLK(LH)

0.2290

0.0860


Constraint Pin

Related Pin

Minimum Pulse Width(ns)

CLK(LHL)

CLK(LH)

0.3000

CLK(LHL)

CLK(LH)

0.4950

CLK(HLH)

CLK(HL)

0.5530

CLK(HLH)

CLK(HL)

0.3570


PIN CAPACITANCE (pf)

Pin

Type

Capacitance (pf)

CLK

input

0.0032

D

input

0.0024


DELAY AND OUTPUT TRANSITION TIME corresponding to min slew and load

Input Pin

Output

When Condition

Tin (ns)

Out Load (pf)

Delay (ns)

Tout (ns)

CLK(LH)

Q(HL)

!D

0.0100

0.0010

0.5998

0.0392

CLK(LH)

Q(LH)

D

0.0100

0.0010

0.6763

0.0466


DYNAMIC ENERGY

Input Pin

When Condition

Tin (ns)

Output

Out Load (pf)

Energy (uW/MHz)

CLK

!D

0.0100

Q(HL)

0.0010

0.4882

CLK

D

0.0100

Q(LH)

0.0010

0.4972

D(LH)

!CLK

0.0100

n/a

n/a

0.1085

D(LH)

CLK

0.0100

n/a

n/a

-0.0067

CLK(LH)

!D

0.0100

n/a

n/a

0.2146

CLK(LH)

D

0.0100

n/a

n/a

0.2140

D(HL)

!CLK

0.0100

n/a

n/a

0.1615

D(HL)

CLK

0.0100

n/a

n/a

0.0096

CLK(HL)

!D

0.0100

n/a

n/a

0.2837

CLK(HL)

D

0.0100

n/a

n/a

0.2878


LEAKAGE POWER

When Condition

Power (nW)

!CLK&!D

0.3482

!CLK&D

0.3748

CLK&!D

0.4405

CLK&D

0.4693