gf180mcu_fd_ip_sram__sram256x8m8wm1

gf180mcu_fd_ip_sram__sram256x8m8wm1

180nm 5V Green synchronous single port SRAM

Memory Macro IP

Datasheet

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Features

• Uses 180nm 5V Green CMOS 13.5um2 6 transistors bitcell

• 256 words X 8 bits, mux 8 Instance

• Periphery circuitry uses 5V transistors

• Operating voltage is 1.62V to 5.50V

• Operating temperature is -40 degC to 125 degC

• Minimum 3 layers of metals required: Metal1, Metal2, Metal3

• Bit write mask

• Self timed operation to reduce power

• Separate data in and data out ports

• Macro cell name: gf180mcu_fd_ip_sram__sram256x8m8wm1

1.0 Pins Description

Signal	Direction	Description
CLK	Input	Clock for the memory. Rising edge triggers operation. All inputs are latched at rising edge of the clock signal
CEN	Input	Memory Enable, Active Low. When CEN is Low, the memory is enabled. When CEN input is High, the memory is deactivated but internal states are retained. CEN must be high before 1st running cycle.
A[6:0]	Input	Address Input. This Address input port is used to address the location to be written during the write cycle and read during the read cycle.
GWEN	Input	Write Enable Input. The RAM is in write cycle when GWEN is low. The RAM is in read cycle when GWEN is high.
WEN[7:0]	Input	Bit Write Mask, Active Low. When the memory is in the write cycle, selectively write into individual outputs are controlled by WEN[7:0]. For example, if CEN, GWEN, WEN[0] are low and WEN[7:1] are high, only D[0] will write into the addressed location and D[7:1] will be ignored during CLK low to high transition.
D[7:0]	Input	Data input bus. The data input bus is used to write data into the memory location specified by address input port during the write cycle.
Q[7:0]	output	Data output bus. It outputs the contents of the memory location addressed by the Address Input signals.
VDD	Power	Power pin.
VSS	Ground	Ground pin.

2.0 Truth Table

CLK	CEN	GWEN	WEN	A	D	Q	status
	H	X	X	X	X	Hold previous data	Standby mode
	L	H	X	A	X	Q	Read mode
	L	L	H	A	D	Hold previous data	Write mode
	L	L	L	A	D	Hold previous data	Mask mode
other	X	X	X	X	X	Hold previous data	Unchanged

Note

X: don’t care

3.0 Capacitance loading ( fF ) @ TT, 25°c

Voltage	CLK	CEN	GWEN	WEN	A	D
5.0v	298.056	18.2857	49.4975	7.84667	40.4163	16.4131
3.3v	293.631	18.3651	48.0112	7.649	40.4958	16.3071
1.8v	282.773	18.3483	44.3232	7.15846	40.4789	16.0437

4.0 Power Consumption ( uW )

Condition of AC Write power is all data input pins switch and AC Read power is all address input and data output pins switch at 1MHz

4.1 5.0V Power

Condition	DC standby	AC Write	AC Read
TT corner, 5.00v, 25°c	0.00034	939.625	841.225
SS corner, 4.50v, -40°c	0.00028	735.458	662.67
SS corner, 4.50v, 125°c	0.00034	761.49	693.63
FF corner, 5.50v, 125°c	0.01866	1195.51	1079.29
FF corner, 5.50v, -40°c	0.00041	1140.56	1025.26

4.2 3.3V Power

Condition	DC standby	AC Write	AC Read
TT corner, 3.3v, 25°c	0.00015	375.012	338.663
SS corner, 3.0v, -40°c	0.00012	300.42	275.565
SS corner, 3.6v, 125°c	0.00016	318.3	288.78
FF corner, 3.6v, 125°c	0.00732	478.296	430.812
FF corner, 3.6v, -40°c	0.00018	446.67	403.308

4.3 1.8V Power

Condition	DC standby	AC Write	AC Read
TT corner, 1.8v, 25°c	0.00004	102.006	93.51
SS corner, 1.62v, -40°c	0.00004	81.2349	75.087
SS corner, 1.62v, 125°c	0.00005	86.0949	79.1103
FF corner, 1.98v, 125°c	0.00236	130.858	119.087
FF corner,1.98v, -40°c	0.00005	120.602	110.454

5.0 AC Characteristics

The timing and power values measured from the input slew of 20ps on clock pin, 20ps on signal and output load .01pF.

5.1 5.0V AC Characteristics

Symbol	Parameter Description	SNSP Process 4.5v, -40C	SNSP Process 4.5v, 125C	Typical Process 5.0v, 25C	FNFP Process 5.5v, 125C	FNFP Process 5.5v, -40C	unit
Tcyc	Min clock period	7.5946	11	6.1181	5.6608	3.957	ns
Tckh	Min clock high time	3.3401	5.4009	2.6907	2.0829	1.4546	ns
Tckl	Min clock low time	3.5036	4.9693	2.6661	1.9737	1.5862	ns
Tcsl	CEN set up time ( CEN = L )	0.4584	0.5869	0.406	0.3883	0.3228	ns
Tchl	CEN hold time ( CEN = L )	1.2328	1.8527	1.1081	1.0768	0.7655	ns
Tcsh	CEN set up time ( CEN = H )	0.5124	0.6616	0.435	0.411	0.3369	ns
Tchh	CEN hold time ( CEN = H )	1.2868	1.9188	1.1371	1.0995	0.7797	ns
Twsl	GWEN set up time ( GWEN = L )	0.718	1.0143	0.6281	0.5888	0.4541	ns
Twhl	GWEN hold time ( GWEN = L )	1.0062	1.3936	0.8467	0.8056	0.6051	ns
Twsh	GWEN set up time ( GWEN = H )	0.6753	0.9358	0.5903	0.5619	0.4329	ns
Twhh	GWEN hold time ( GWEN = H )	0.5421	0.712	0.4752	0.4717	0.3744	ns
Twisl	WEN set up time ( WEN = L )	0.2681	0.3326	0.2552	0.2318	0.2132	ns
Twihl	WEN hold time ( WEN = L )	1.0093	1.3936	0.8467	0.8056	0.6051	ns
Twish	WEN set up time ( WEN = H )	0	0	0	0	0	ns
Twihh	WEN hold time ( WEN = H )	0.5428	0.7142	0.4752	0.4717	0.3744	ns
Tasl	A set up time ( A = L )	0.8176	1.0609	0.6825	0.6069	0.4999	ns
Tahl	A hold time ( A = L )	0.6347	0.8154	0.5351	0.4936	0.4026	ns
Tash	A set up time ( A = H )	0.6116	0.8236	0.5149	0.4745	0.3738	ns
Tahh	A hold time ( A = H )	0.6556	0.8491	0.5475	0.5017	0.4073	ns
Tdsl	D set up time ( D = L )	0.1068	0.0793	0.1079	0.0931	0.1215	ns
Tdhl	D hold time ( D = L )	0.5319	0.6948	0.4699	0.4799	0.3698	ns
Tdsh	D set up time ( D = H )	0.5818	0.7537	0.4744	0.4028	0.3544	ns
Tdhh	D hold time ( D= H )	0.7624	1.0445	0.659	0.6446	0.491	ns
Tah	Clock high to Q high	5.5913	8.2512	4.5692	4.2569	2.9344	ns
Tal	Clock high to Q low	5.7745	8.5132	4.7158	4.3699	3.025	ns

5.2 3.3V AC Characteristics

Symbol	Parameter description	SNSP Process 3.0v, -40C	SNSP Process 3.0, 125C	Typical Process 3.3v, 25C	FNFP Process 3.6v, 125C	FNFP Process 3.6v, -40C	unit
Tcyc	Min clock period	11.6044	17.0863	8.5597	7.3978	5.1007	ns
Tckh	Min clock high time	4.1518	5.1878	3.2873	2.8975	1.8998	ns
Tckl	Min clock low time	4.2752	6.2768	3.891	2.9738	1.8573	ns
Tcsl	CEN set up time ( CEN = L )	0.6591	0.8517	0.542	0.4951	0.4047	ns
Tchl	CEN hold time ( CEN = L )	1.9054	2.849	1.592	1.4784	1.0184	ns
Tcsh	CEN set up time ( CEN = H )	0.8058	1.0775	0.6175	0.5341	0.4262	ns
Tchh	CEN hold time ( CEN = H )	2.0065	2.9742	1.64	1.5046	1.0375	ns
Twsl	GWEN set up time ( GWEN = L )	1.1586	1.6455	0.9198	0.8113	0.6012	ns
Twhl	GWEN hold time ( GWEN = L )	1.4693	2.0948	1.1528	1.039	0.7639	ns
Twsh	GWEN set up time ( GWEN = H )	1.0285	1.4295	0.8241	0.741	0.5578	ns
Twhh	GWEN hold time ( GWEN = H )	0.7347	1.0252	0.6061	0.5779	0.4516	ns
Twisl	WEN set up time ( WEN = L )	0.4276	0.4945	0.36	0.3185	0.2767	ns
Twihl	WEN hold time ( WEN = L )	1.47	2.0958	1.1533	1.039	0.7639	ns
Twish	WEN set up time ( WEN = H )	0	0	0	0	0	ns
Twihh	WEN hold time ( WEN = H )	0.7364	1.0252	0.6064	0.5779	0.4516	ns
Tasl	A set up time ( A = L )	1.2239	1.5436	0.9321	0.793	0.634	ns
Tahl	A hold time ( A = L )	0.883	1.1501	0.6944	0.6117	0.4942	ns
Tash	A set up time ( A = H )	0.9765	1.2625	0.7394	0.6387	0.497	ns
Tahh	A hold time ( A = H )	0.9455	1.2363	0.7301	0.6353	0.5077	ns
Tdsl	D set up time ( D = L )	0.151	0.0675	0.1406	0.1223	0.1528	ns
Tdhl	D hold time ( D = L )	0.6331	0.8795	0.5685	0.56	0.4337	ns
Tdsh	D set up time ( D = H )	0.9896	1.2399	0.694	0.5587	0.4635	ns
Tdhh	D hold time ( D= H )	1.1116	1.5609	0.8826	0.8138	0.6107	ns
Tah	Clock high to Q high	8.6801	12.588	6.501	5.6753	3.8609	ns
Tal	Clock high to Q low	9.039	13.1052	6.7522	5.8621	3.994	ns

5.3 1.8V AC Characteristics

Symbol	Parameter description	SNSP Process 1.62v, -40C	SNSP Process 1.62v, 125C	Typical Process 1.8v, 25C	FNFP Process 1.98v, 125C	FNFP Process 1.98v, -40C	unit
Tcyc	Min clock period	49.6236	53.6235	22.4703	14.439	10.5548	ns
Tckh	Min clock high time	18.4434	25.7785	10.9148	3.8319	4.6646	ns
Tckl	Min clock low time	24.2445	20.8014	10.2887	5.3502	4.7431	ns
Tcsl	CEN set up time ( CEN = L )	2.3681	2.4651	1.1518	0.7912	0.6521	ns
Tchl	CEN hold time ( CEN = L )	7.2637	8.1415	3.8285	2.745	1.9932	ns
Tcsh	CEN set up time ( CEN = H )	3.5818	3.6043	1.5568	0.9701	0.7982	ns
Tchh	CEN hold time ( CEN = H )	8.1245	8.8521	4.0462	2.8098	2.0519	ns
Twsl	GWEN set up time ( GWEN = L )	5.3918	5.595	2.4131	1.5312	1.1886	ns
Twhl	GWEN hold time ( GWEN = L )	6.6902	7.1843	2.641	1.7922	1.3425	ns
Twsh	GWEN set up time ( GWEN = H )	3.788	4.1484	1.8898	1.3037	1.0054	ns
Twhh	GWEN hold time ( GWEN = H )	3.9825	4.2086	1.3454	0.9058	0.7109	ns
Twisl	WEN set up time ( WEN = L )	0	0	0.635	0.5269	0.4594	ns
Twihl	WEN hold time ( WEN = L )	6.7241	7.2059	2.6513	1.7922	1.345	ns
Twish	WEN set up time ( WEN = H )	0	0	0	0	0	ns
Twihh	WEN hold time ( WEN = H )	3.9825	4.2086	1.3498	0.9058	0.7109	ns
Tasl	A set up time ( A = L )	2.5026	2.5937	1.8544	1.345	1.102	ns
Tahl	A hold time ( A = L )	2.4783	2.6941	1.3189	0.9519	0.7682	ns
Tash	A set up time ( A = H )	3.5235	3.5752	1.5839	1.1347	0.92	ns
Tahh	A hold time ( A = H )	3.0774	3.2544	1.517	1.0314	0.8371	ns
Tdsl	D set up time ( D = L )	0	0	0	0.1068	0.1609	ns
Tdhl	D hold time ( D = L )	3.233	3.3177	1.0226	0.7713	0.5799	ns
Tdsh	D set up time ( D = H )	3.2797	3.1593	1.7976	1.0285	0.9057	ns
Tdhh	D hold time ( D= H )	5.9233	6.148	2.1673	1.38	1.0712	ns
Tah	Clock high to Q high	34.2708	37.734	16.1892	10.6138	7.8157	ns
Tal	Clock high to Q low	36.8388	39.9912	17.106	11.0951	8.1864	ns

AC Timing Waveform Chart

6.0 Physical Dimensions

Width(um)	Height(um)	Area(um^2)
431.86	340.88	147212.4368