gf180mcu_fd_ip_sram__sram128x8m8wm1

gf180mcu_fd_ip_sram__sram128x8m8wm1

180nm 5V Green synchronous single port SRAM

Memory Macro IP

Datasheet

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Features

• Uses 180nm 5V Green CMOS 13.5um2 6 transistors bitcell

• 128 words X 8 bits, mux 8 Instance

• Periphery circuitry uses 5V transistors

• Operating voltage is 1.62V to 5.50V

• Operating temperature is -40 degC to 125 degC

• Minimum 3 layers of metals required: Metal1, Metal2, Metal3

• Bit write mask

• Self timed operation to reduce power

• Separate data in and data out ports

• Macro cell name: gf180mcu_fd_ip_sram__sram128x8m8wm1

1.0 Pins Description

Signal	Direction	Description
CLK	Input	Clock for the memory. Rising edge triggers operation. All inputs are latched at rising edge of the clock signal
CEN	Input	Memory Enable, Active Low. When CEN is Low, the memory is enabled. When CEN input is High, the memory is deactivated but internal states are retained. CEN must be high before 1st running cycle.
A[6:0]	Input	Address Input. This Address input port is used to address the location to be written during the write cycle and read during the read cycle.
GWEN	Input	Write Enable Input. The RAM is in write cycle when GWEN is low. The RAM is in read cycle when GWEN is high.
WEN[7:0]	Input	Bit Write Mask, Active Low. When the memory is in the write cycle, selectively write into individual outputs are controlled by WEN[7:0]. For example, if CEN, GWEN, WEN[0] are low and WEN[7:1] are high, only D[0] will write into the addressed location and D[7:1] will be ignored during CLK low to high transition.
D[7:0]	Input	Data input bus. The data input bus is used to write data into the memory location specified by address input port during the write cycle.
Q[7:0]	output	Data output bus. It outputs the contents of the memory location addressed by the Address Input signals.
VDD	Power	Power pin.
VSS	Ground	Ground pin.

2.0 Truth Table

CLK	CEN	GWEN	WEN	A	D	Q	status
	H	X	X	X	X	Hold previous data	Standby mode
	L	H	X	A	X	Q	Read mode
	L	L	H	A	D	Hold previous data	Write mode
	L	L	L	A	D	Hold previous data	Mask mode
other	X	X	X	X	X	Hold previous data	Unchanged

Note

X: don’t care

3.0 Capacitance loading ( fF ) @ TT, 25°c

Voltage	CLK	CEN	GWEN	WEN	A	D
5.0v	298.116	17.4878	49.6559	7.84667	38.8545	16.7359
3.3v	293.691	17.5673	48.1696	7.649	38.934	16.7013
1.8v	282.833	17.5504	44.4816	7.15846	38.9171	16.0438

4.0 Power Consumption ( uW )

Condition of AC Write power is all data input pins switch and AC Read power is all address input and data output pins switch at 1MHz

4.1 5.0V Power

Condition	DC standby	AC Write	AC Read
TT corner, 5.00v, 25°c	0.0002	897.5	805.25
SS corner, 4.50v, -40°c	0.00016	702.945	632.295
SS corner, 4.50v, 125°c	0.00021	731.97	662.018
FF corner, 5.50v, 125°c	0.01252	1146.72	1036.97
FF corner, 5.50v, -40°c	0.00024	1091.34	983.758

4.2 3.3V Power

Condition	DC standby	AC Write	AC Read
TT corner, 3.3v, 25°c	0.00009	357.571	324.472
SS corner, 3.0v, -40°c	0.00007	284.31	262.08
SS corner, 3.6v, 125°c	0.0001	303.885	276.39
FF corner, 3.6v, 125°c	0.00491	460.764	413.478
FF corner, 3.6v, -40°c	0.0001	427.68	386.604

4.3 1.8V Power

Condition	DC standby	AC Write	AC Read
TT corner, 1.8v, 25°c	0.00003	96.498	88.7733
SS corner, 1.62v, -40°c	0.00002	76.3255	70.9123
SS corner, 1.62v, 125°c	0.00003	81.5346	74.767
FF corner, 1.98v, 125°c	0.00159	125.948	114.038
FF corner,1.98v, -40°c	0.00003	115.503	105.088

5.0 AC Characteristics

The timing and power values measured from the input slew of 20ps on clock pin, 20ps on signal and output load .01pF.

5.1 5.0V AC Characteristics

Symbol	Parameter Description	SNSP Process 4.5v, -40C	SNSP Process 4.5v, 125C	Typical Process 5.0v, 25C	FNFP Process 5.5v, 125C	FNFP Process 5.5v, -40C	unit
Tcyc	Min clock period	7.2968	10.5483	5.8805	5.4403	3.8099	ns
Tckh	Min clock high time	2.557	4.5174	2.2464	2.1763	1.411	ns
Tckl	Min clock low time	2.5652	4.5311	2.3734	2.3048	1.3029	ns
Tcsl	CEN set up time ( CEN = L )	0.459	0.5874	0.4066	0.3895	0.3233	ns
Tchl	CEN hold time ( CEN = L )	1.2324	1.8522	1.1095	1.0791	0.7647	ns
Tcsh	CEN set up time ( CEN = H )	0.5119	0.6595	0.4349	0.411	0.3372	ns
Tchh	CEN hold time ( CEN = H )	1.2853	1.9179	1.1378	1.1006	0.7786	ns
Twsl	GWEN set up time ( GWEN = L )	0.7164	1.014	0.6277	0.5876	0.4544	ns
Twhl	GWEN hold time ( GWEN = L )	0.9936	1.3718	0.8367	0.7948	0.5965	ns
Twsh	GWEN set up time ( GWEN = H )	0.6741	0.9339	0.5892	0.5612	0.4344	ns
Twhh	GWEN hold time ( GWEN = H )	0.5303	0.6896	0.4644	0.4611	0.3654	ns
Twisl	WEN set up time ( WEN = L )	0.2801	0.3526	0.2642	0.2408	0.2218	ns
Twihl	WEN hold time ( WEN = L )	0.9957	1.3718	0.8367	0.7948	0.5965	ns
Twish	WEN set up time ( WEN = H )	0	0	0	0	0	ns
Twihh	WEN hold time ( WEN = H )	0.5303	0.6924	0.4646	0.4611	0.3654	ns
Tasl	A set up time ( A = L )	0.8834	1.1569	0.7313	0.6558	0.5337	ns
Tahl	A hold time ( A = L )	0.6364	0.8155	0.5345	0.4939	0.4013	ns
Tash	A set up time ( A = H )	0.6186	0.8442	0.5154	0.4813	0.3834	ns
Tahh	A hold time ( A = H )	0.6573	0.8495	0.5472	0.5023	0.4071	ns
Tdsl	D set up time ( D = L )	0.1168	0.099	0.1188	0.1022	0.1285	ns
Tdhl	D hold time ( D = L )	0.5183	0.6714	0.4622	0.472	0.3631	ns
Tdsh	D set up time ( D = H )	0.5947	0.7737	0.4831	0.4111	0.359	ns
Tdhh	D hold time ( D= H )	0.7521	1.0224	0.6506	0.6352	0.4843	ns
Tah	Clock high to Q high	5.399	7.9528	4.4262	4.1233	2.8427	ns
Tal	Clock high to Q low	5.5834	8.2156	4.5722	4.2356	2.93	ns

5.2 3.3V AC Characteristics

Symbol	Parameter description	SNSP Process 3.0v, -40C	SNSP Process 3.0, 125C	Typical Process 3.3v, 25C	FNFP Process 3.6v, 125C	FNFP Process 3.6v, -40C	unit
Tcyc	Min clock period	11.287	16.6365	8.4053	7.2375	4.8961	ns
Tckh	Min clock high time	3.6774	4.7153	2.7639	2.5493	2.4443	ns
Tckl	Min clock low time	4.4364	5.9546	2.8652	3.328	1.9857	ns
Tcsl	CEN set up time ( CEN = L )	0.6575	0.8523	0.5421	0.4968	0.4053	ns
Tchl	CEN hold time ( CEN = L )	1.9064	2.8563	1.594	1.4782	1.0188	ns
Tcsh	CEN set up time ( CEN = H )	0.8066	1.0749	0.6133	0.5368	0.4259	ns
Tchh	CEN hold time ( CEN = H )	2.0101	2.9791	1.6398	1.5029	1.0368	ns
Twsl	GWEN set up time ( GWEN = L )	1.1592	1.6428	0.9199	0.8121	0.5999	ns
Twhl	GWEN hold time ( GWEN = L )	1.4433	2.0627	1.138	1.024	0.7538	ns
Twsh	GWEN set up time ( GWEN = H )	1.0287	1.4302	0.8238	0.742	0.557	ns
Twhh	GWEN hold time ( GWEN = H )	0.7157	0.9902	0.592	0.5628	0.4407	ns
Twisl	WEN set up time ( WEN = L )	0.441	0.5252	0.3732	0.3322	0.287	ns
Twihl	WEN hold time ( WEN = L )	1.4443	2.0643	1.138	1.024	0.7538	ns
Twish	WEN set up time ( WEN = H )	0	0	0	0	0	ns
Twihh	WEN hold time ( WEN = H )	0.7158	0.9902	0.592	0.5628	0.4407	ns
Tasl	A set up time ( A = L )	1.32	1.6823	1.0068	0.8583	0.6762	ns
Tahl	A hold time ( A = L )	0.8788	1.1411	0.6955	0.6157	0.4954	ns
Tash	A set up time ( A = H )	0.9908	1.2941	0.7507	0.6486	0.5052	ns
Tahh	A hold time ( A = H )	0.9417	1.2293	0.7292	0.637	0.5084	ns
Tdsl	D set up time ( D = L )	0.1738	0.1041	0.156	0.1357	0.1612	ns
Tdhl	D hold time ( D = L )	0.6128	0.8611	0.5512	0.5437	0.4224	ns
Tdsh	D set up time ( D = H )	1.0132	1.2631	0.7156	0.5732	0.4724	ns
Tdhh	D hold time ( D= H )	1.0883	1.5344	0.8666	0.8014	0.5999	ns
Tah	Clock high to Q high	8.3652	12.1944	6.298	5.501	3.7381	ns
Tal	Clock high To Q low	8.7238	12.7032	6.5484	5.6867	3.873	ns

5.3 1.8V AC Characteristics

Symbol	Parameter description	SNSP Process 1.62v, -40C	SNSP Process 1.62v, 125C	Typical Process 1.8v, 25C	FNFP Process 1.98v, 125C	FNFP Process 1.98v, -40C	unit
Tcyc	Min clock period	48.0305	51.9626	21.8315	14.0727	10.2767	ns
Tckh	Min clock high time	21.8197	13.4605	10.6663	3.7733	2.6968	ns
Tckl	Min clock low time	22.5675	21.362	10.6844	5.1485	3.7226	ns
Tcsl	CEN set up time ( CEN = L )	2.3724	2.4562	1.1519	0.8005	0.6534	ns
Tchl	CEN hold time ( CEN = L )	7.2717	8.1123	3.8274	2.746	2.0001	ns
Tcsh	CEN set up time ( CEN = H )	3.5899	3.621	1.5559	0.9713	0.7968	ns
Tchh	CEN hold time ( CEN = H )	8.1139	8.8496	4.0504	2.8068	2.0571	ns
Twsl	GWEN set up time ( GWEN = L )	5.4203	5.5914	2.4142	1.5341	1.1897	ns
Twhl	GWEN hold time ( GWEN = L )	6.5279	7.0068	2.5795	1.764	1.3151	ns
Twsh	GWEN set up time ( GWEN = H )	3.7875	4.1574	1.8835	1.3011	1.0048	ns
Twhh	GWEN hold time ( GWEN = H )	3.7942	4.0118	1.2881	0.8686	0.6835	ns
Twisl	WEN set up time ( WEN = L )	0	0.0413	0.6956	0.5569	0.4878	ns
Twihl	WEN hold time ( WEN = L )	6.5574	7.0283	2.5901	1.764	1.3173	ns
Twish	WEN set up time ( WEN = H )	0	0	0	0	0	ns
Twihh	WEN hold time ( WEN = H )	3.8062	4.024	1.2894	0.8686	0.6835	ns
Tasl	A set up time ( A = L )	2.7688	2.9848	2.0331	1.4547	1.1882	ns
Tahl	A hold time ( A = L )	2.4697	2.6801	1.3163	0.9482	0.7648	ns
Tash	A set up time ( A = H )	3.5404	3.5743	1.6536	1.1654	0.9602	ns
Tahh	A hold time ( A = H )	3.0635	3.2382	1.5118	1.0362	0.8406	ns
Tdsl	D set up time ( D = L )	0	0	0.0154	0.1334	0.1847	ns
Tdhl	D hold time ( D = L )	3.0741	3.1426	0.9688	0.7561	0.5574	ns
Tdsh	D set up time ( D = H )	3.4192	3.2969	1.8301	1.0588	0.9275	ns
Tdhh	D hold time ( D= H )	5.7672	5.9734	2.1079	1.3541	1.0484	ns
Tah	Clock high to Q High	32.9568	36.3012	15.606	10.2752	7.5431	ns
Tal	Clock high To Q low	35.4984	38.5848	16.5192	10.751	7.9138	ns

AC Timing Waveform Chart

6.0 Physical Dimensions

Width(um)	Height(um)	Area(um^2)
431.86	268.88	116118.5168